1. Field of the Invention
Embodiments of the present invention relate to the electrical testing of semiconductor devices, and more particularly, to an automatic test equipment (ATE) used for electrically testing semiconductor devices.
2. Description of the Related Art
Semiconductor devices are produced in a wafer state, assembled into semiconductor packages, and electrically tested, before being delivered to users. Because semiconductor memory devices such as dynamic random access memory (DRAM) have gained high capacity, high speed, and many pins, the efficiency of their electrical test processes must be increased. To increase the efficiency of the electrical test processes, testers focus on higher speed testing and improvement of throughput time.
Test throughput time can normally be improved in a number of ways. One way is by controlling a test program. Another way is to increase the number of semiconductor memory devices that can be tested simultaneously, i.e. by testing an increased number of devices in parallel. Finally, improvement of throughput time can be achieved by performing a high-speed test in the hardware of the automatic test equipment. Embodiments of the present invention are directed to improving high-speed test efficiency in the hardware of the automatic test equipment.
FIG. 1 is a schematic block diagram of an automatic test equipment body for testing a typical semiconductor memory device.
Referring to FIG. 1, an electrical test is performed to screen defects generated in wafer manufacturing or assembling processes and to identify and remove the defective products. For such electrical tests, an automatic test equipment (ATE) includes an ATE body 100, a socket board 200 as an interface board, and a handler to effectively load a device under test (DUT) 300.
The ATE body 100 includes a tester processor 110 to control hardware components which are built into the ATE. The hardware components may be a programmable power supply 112, a direct current (DC) parameter measurement unit 114, an algorithmic pattern generator 116, a timing generator 118, a wave sharp formatter 120, and pin electronics 150 including a driver and a comparator. Accordingly, the ATE body 100 tests electrical functions of the DUT 300 which is connected to the pin electronics 150 through the socket board 200, while the hardware components communicate signals with each other according to test programs operating in the tester processor 110.
Meanwhile, a test program includes a DC test, an alternating current (AC) test, and a function test. The function test checks functions under actual operating conditions of a semiconductor memory device such as a DRAM. The function test writes input signals created by the algorithmic pattern generator 116, the timing generator 118 and the wave shape formatter 120 of the ATE 100, to the DUT 300, e.g. the DRAM (Write operation), and reads out the written data from the DRAM (Read operation) to identify a defective semiconductor device using a comparator, by comparing the output with the expected patterns.
FIG. 2 is a block diagram of a field programmable gate array (FPGA) controlling a driver and a comparator built into a conventional ATE body.
Referring to FIG. 2, in an electrical test for a DRAM, an ATE body controls signals of a driver 130 and a comparator 140 using a semiconductor device having a function of an FPGA 160. The FPGA 160 is an application specific integrated circuit (ASIC) type semiconductor device which can program logic circuits according to a user's demand.
Accordingly, when signal patterns are transferred from the algorithmic pattern generator 116 and the timing generator 118 to terminals of the driver 130 and the comparator 140 of the FPGA 160, the FPGA 160 controls and transfers the signals to DUT 300.
Typically, the FPGA 160 controls the driver 130 and the comparator 140, and thus the maximum operating frequency of the ATE cannot be greater than that of the FPGA 160. For example, if the maximum operating frequency of the FPGA 160 is 400 MHz, DDR2 or DDR3 type DRAM having a maximum operating frequency of more than 400 MHz cannot be electrically tested using this configuration. The capacitance of the semiconductor including FPGA circuits mainly prevent the maximum operating frequency of the FPGA 160 from being greater than 400 MHz in contemporary systems, which limits the capability of ATE systems.